IICEN=0, MST=0, WUEN=0, TX=0, IICIE=0, TXAK=0, DMAEN=0
I2C Control Register 1
| DMAEN | DMA enable 0 (0): All DMA signalling disabled. 1 (1): DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. |
| WUEN | Wakeup enable 0 (0): Normal operation. No interrupt generated when address matching in low power mode. 1 (1): Enables the wakeup function in low power mode. |
| RSTA | Repeat START |
| TXAK | Transmit acknowledge enable 0 (0): An acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is set) receiving byte. 1 (1): No acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is set) receiving data byte.SCL is held low until TXAK is written. |
| TX | Transmit mode select 0 (0): Receive 1 (1): Transmit |
| MST | Master mode select 0 (0): Slave mode 1 (1): Master mode |
| IICIE | I2C interrupt enable 0 (0): Disabled 1 (1): Enabled |
| IICEN | I2C enable 0 (0): Disabled 1 (1): Enabled |